1. Field of the Invention
Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems.
2. Description of the Related Art
High speed serializer/deserializer (HSS) cores are an important part of application-specific integrated circuit (ASIC) product offering. These cores are used in conjunction with other ASIC cores to implement protocols such as XAUI, PCI Express, Serial ATA, FibreChannel, Infiniband, etc. However, the number of signal pins associated with these cores, as well as the functional complexity associated with these cores, continues to present a challenge to chip designers who must instantiate these HSS cores and associated protocol cores and connect all of the signals. Such issues were partially addressed by the invention described in U.S. patent application Ser. No. 10/709,528, now U.S. Pat. No. 7,290,238 (incorporated herein by reference), which described a means of developing a set of inference rules to facilitate automated wiring of an HSS subsystem. Having generated such a subsystem in an automated fashion, it is also desirable to generate a simulation testbench capable of verifying the connections of the subsystem.